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KiCad Like a Pro 3e – eBook

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  1. eBook status
    1 Lecture
  2. 00 - Front matter
    5 Lectures
  3. 01 - Getting started with PCB design
    6 Lectures
  4. 02 – Getting started with KiCad
    12 Lectures
  5. 03 - Project: A hands-on tour of KiCad - Schematic Design
    11 Lectures
  6. 04 - Project: A hands-on tour of KiCad - Layout
    10 Lectures
  7. 05 - Design principles and PCB terms
    16 Lectures
  8. 06 - PCB design workflows
    17 Lectures
  9. 07 - Fundamental Kicad how-to: Symbols and Eeschema
    17 Lectures
  10. 08 - Fundamental Kicad how-to: Footprints and Pcbnew
    31 Lectures
  11. 09 - Project: Design a simple breadboard power supply PCB
    23 Lectures
  12. 10 - Project: A 4 x 8 x 8 LED matrix array clock
    25 Lectures
  13. 11 - Project: MCU datalogger with build-in 512K EEPROM and clock
    37 Lectures
  14. 12 - Project: An ESP32 clone
    25 Lectures
  15. 13 - Recipes
    56 Lectures
  16. 14 - What's new in KiCad 7
    14 Lectures
  17. XX – Content by contributing authors
    4 Lectures
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In this chapter, you will complete step six of the schematic design workflow, that you learned about in the second chapter of this part of the book. This chapter will show you how to use the Eeschema electrical rules checker (ERC) tool to ensure that your schematic does not contain errors that should be corrected before continuing with the layout workflow.

To use the ERC, invoke it by clicking on its button in the top toolbar or the Inspect menu (Figure 3.10.1).

Figure 3.10.1: Starting the ERC tool.

The ERC window will appear (see Figure 3.10.2 below). You can run the check immediately by clicking on “Run ERC” (1). The results in my example show zero errors and warnings (see box below). You can click on the Violations (2) and Messages (3) tabs to switch between the two types of output that the ERC can provide. You can also use the checkboxes at the bottom of the window to enable or disable the various message types.

Figure 3.10.2: The ERC window.

Of course, we are working on a simple circuit, and I did not make any mistakes during the schematic workflow steps. I will deliberately delete the wire that connects the resistor to the switch and rerun the ERC. This time, the ERC reveals two violations (Figure 3.10.2):

Figure 3.10.2: The ERC reveals two violations.

When you click on a violation in the ERC, the schematic editor in the background will pan to show you the location of the violation. There are also markers (arrows) that give you a visual clue as to its location. Use all the information that the ERC gives you to find and fix these violations before you continue. In the example above, the deleted wire caused two pins to be left unconnected. This is why the ERC lists the unconnected pins instead of the missing wire as the violation.

Go ahead and fix the violations by restoring the wire. Re-run the ERC to make sure that there are no remaining violations. Now that the ERC passes, there is one step left in the schematic design process. In this step, I will add comments and graphics to the schematic. This is the equivalent of adding explanatory comments to software source code. Let’s complete step seven in the next chapter.